x86 & Arm Rival, RISC-V Architecture Ships 10 Billion Cores

x86 & Arm Rival, RISC-V Architecture Ships 10 Billion Cores

Calista Redmond, CEO of RISC-V International, announced at Embedded World that there are currently ten billion RISC-V cores in the marketplace.

ARM RISC-V architecture has shipped 10 billion cores, reported to be more prominent than x86 & Arm architecture for the future

RISC-V, pronounced as “risk five,” is an open-standard instruction set architecture (ISA) supplied under open-source licenses that are free for use. The base set of instructions has 32-bit fixed-length naturally aligned instructions, and the ISA endorses variable-length extensions, meaning that each instruction can be any numeral length within 16-bit parcels. The instruction set comes in 32-bit and 64-bit address space flavors and is created for an expansive range of usages. Various subsets back everything from diminutive embedded systems to PCs to supercomputers with vector processors to warehouse-scale rack-mounted parallel computers.

Calista Redmond said that open standards are the key.

Linux is doing this for software, and we are doing this for hardware. We estimate that there are 10 billion RISC-V cores on the market.

But, the path to ten billion was no quick task. It is reported that seventeen years of trial and error for the ARM architecture took to achieve the milestone in 2008. On the other hand, RISC-V only took twelve years to complete ten billion. Redmond anticipates that the number of RISC-V processor cores is predicted to achieve eighty billion by 2025.

Source: Embedded World 2022.

Included with this news was the announcement of the consent of the new four specifications and extensions starting this year. The four new specifications are:

  • RISC-V specification for SBI architects a firmware layer between the hardware platform and the operating system kernel using an application binary interface in supervisor mode (S-mode or VS-mode). This abstraction enables common platform services across all RISC-V operating system implementations. Many RISC-V members have already implemented the RISC-V SBI specification in their RISC-V solutions, so ratifying the specification will ensure a standard approach across the entire RISC-V ecosystem, ensuring compatibility. Development and ratification of this specification were led by Atish Patra of Rivos, with work conducted by the Platform Horizontal Steering Committee.
  • RISC-V UEFI Protocols bring existing UEFI standards onto RISC-V platforms. Development and ratification of this specification were led by Sunil V L, Ventana Micro, and Philipp Tomsich, VRULL GmbH, with work conducted in the Privileged Software Technical Working Group.
  • E-Trace for RISC-V defines a highly efficient approach to processor tracing that uses a branch trace, ideal for debugging any type of application from tiny embedded designs to super-powerful computers. E-Trace for RISC-V documentation specifies the signals between the RISC-V core and the encoder (or ingress port), a compressed branch trace algorithm, and a packet format to encapsulate compressed branch trace information. Development and ratification of this specification were led by Gajinder Panesar of Picocom and RISC-V’s E-Trace Task Group.
  • RISC-V Zmmul Multiply Only enables low-cost implementations that require multiplication operations but not division and is part of the RISC-V Unprivileged Specification. Development and ratification of this extension were led by Allen Baum, with work conducted in the Unprivileged ISA Committee.

News Sources: IT Home, RISV.org

#x86 #Arm #Rival #RISCV #Architecture #Ships #Billion #Cores

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